The Senior Digital Designer will be responsible for designing and verifying complex digital circuits and systems. This role involves full ownership of the digital design process, including architectural design, RTL coding, synthesis, and timing closure. The ideal candidate will have extensive experience in digital design methodologies, a deep understanding of verification processes, and a strong ability to work in a collaborative team environment. As a senior member of the team, the candidate will also mentor junior engineers and provide technical leadership.

Key Responsibilities:

• RTL Design: Lead the architectural design, RTL coding (in Verilog/SystemVerilog/VHDL), and synthesis of digital blocks for various SoC or FPGA-based projects.
• Design Verification: Collaborate with the verification team to define and implement verification plans, including developing testbenches and performing simulation-based verification.
• Synthesis and Timing Closure: Execute design synthesis and timing analysis, ensuring designs meet performance, power, and area goals.
• Design Review: Participate in design and code reviews, providing feedback and guidance to improve design quality and efficiency.
• Cross-Functional Collaboration: Work closely with analog/mixed-signal engineers, software teams, and physical design teams to ensure seamless integration and functionality of digital designs.
• Post-Silicon Validation: Support post-silicon validation and debugging by correlating simulation results with silicon performance and resolving issues.
• Mentorship: Provide technical leadership and mentoring to junior designers, helping them grow in their roles and improve their design skills.
• Documentation: Ensure proper documentation of design specifications, verification plans, and other related materials.

Education:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

Experience:

• 7+ years of experience in digital design, including RTL design, verification, and synthesis.
• Proven track record of successfully completing multiple tapeouts in advanced process nodes.

Technical Skills:

• Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog, or VHDL.
• Strong experience with synthesis tools (e.g., Synopsys Design Compiler) and timing analysis tools (e.g., PrimeTime).
• Solid understanding of digital design concepts including FSMs, pipelining, clock gating, and low-power design techniques.
• Familiarity with advanced verification methodologies (e.g., UVM) and tools (e.g., Mentor Questa, Cadence Xcelium).
• Experience in working with advanced process technologies (e.g., 28nm, 14nm, FinFET).
• Understanding of DFT (Design for Test) techniques and scan insertion.
• Familiarity with FPGA-based design and prototyping is a plus.

Behavioral Competencies:

• Technical Leadership: Ability to lead projects and mentor junior team members.
• Problem-Solving: Strong analytical skills to identify and resolve complex design challenges.
• Collaboration: Works effectively in a multidisciplinary team environment, communicating clearly with cross-functional teams.
• Accountability: Takes ownership of deliverables and ensures timely project completion.
• Attention to Detail: Ensures high-quality design, verification, and documentation.

Preferred Skills:

• Experience with low-power design methodologies.
• Knowledge of interface protocols (e.g., I2C, SPI, USB, PCIe, etc.).
• Familiarity with high-level synthesis (HLS) and system-level modeling.